 Functional verification培訓 |
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學員學習本課程應具備下列基礎知識：
◆ 電路系統(tǒng)的基本概念。 |
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班級規(guī)模及環(huán)境--熱線:4008699035 手機:15921673576( 微信同號) |
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每期人數(shù)限3到5人。 |
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上課時間和地點 |
上課地點：【上海】：同濟大學(滬西)/新城金郡商務樓(11號線白銀路站) 【深圳分部】：電影大廈(地鐵一號線大劇院站)/深圳大學成教院 【北京分部】：北京中山學院/福鑫大樓 【南京分部】：金港大廈(和燕路) 【武漢分部】：佳源大廈（高新二路） 【成都分部】：領館區(qū)1號（中和大道） 【沈陽分部】：沈陽理工大學/六宅臻品 【鄭州分部】：鄭州大學/錦華大廈 【石家莊分部】：河北科技大學/瑞景大廈 【廣州分部】：廣糧大廈 【西安分部】：協(xié)同大廈
最近開課時間(周末班/連續(xù)班/晚班）：Functional verification培訓：2020年3月16日 |
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實驗設備 |
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最新優(yōu)惠 |
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◆請咨詢客服。 |
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質量保障 |
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1、培訓過程中，如有部分內容理解不透或消化不好，可免費在以后培訓班中重聽；
2、培訓結束后,授課老師留給學員聯(lián)系方式,保障培訓效果,免費提供課后技術支持。
3、培訓合格學員可享受免費推薦就業(yè)機會。 |
Functional verification培訓
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第一階段 Incisive Comprehensive Coverage
Course Description
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course explores Incisive? comprehensive coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of SystemC, VHDL, Verilog?, and mixed-language designs. Not all coverage features are available with all languages.
The course discusses the collection and analysis of the following types of coverage:
- Code (block, expression, toggle, state, and arc) coverage
- Data-oriented functional coverage using SystemVerilog covergroups
- Control-oriented functional coverage using PSL and SystemVerilog assertions
Learning Objectives
After completing this course you will be able to:
- Effectively use the Incisive comprehensive coverage with your SystemC, VHDL, Verilog, and mixed-language designs
第二階段 Incisive SystemC, VHDL, and Verilog Simulation
Course Description
This course addresses Incisive? mixed-language (SystemC?, VHDL, and Verilog?) event-driven digital simulation. The course takes you through the compilation, elaboration, simulation, and interactive debug process, at each step explaining the most commonly used options. This course treats the SystemC, VHDL, and Verilog languages equivalently. You can do the labs in your choice of language.
Learning Objectives
After completing this course you will be able to:
- Compile, elaborate, link, and simulate a design: Understand how to specify the inputs and outputs at each phase, configure the design, and control each process for effectiveness and optimal performance.
- Debug a design with the textual interactive simulation interface: Briefly examine most of the interactive commands for the purpose of understanding what capabilities are available and how you can use them in a script to drive batched regression tests; practice these capabilities in the context of a scripted debug scenario.
- Debug a design with the graphical interactive simulation interface: Examine many of the capabilities of the feature-rich SimVision graphical simulation analysis environment; practice these capabilities in the context of a scripted debug scenario.
- Utilize some of the other tools available to assist your simulation-related efforts to: Verify your platform's patch level, protect your intellectual property, “l(fā)int” your design and filter and sort the analysis report, manage your library of compiled design objects, compare simulation traces, package your design for transmittal, and much more.
- Optionally: Understand the issues involved with mixed-language instantiation, simulation, and debugging; examine the mechanics of interconnecting components of multiple languages; choose and simulate a mixed-language design configuration containing at least one HDL component and at least one SystemC component.
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