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1. 嵌入式語言之使用 SystemVerilog 進(jìn)行設(shè)計(jì)培訓(xùn)
   ? 使用 SystemVerilog 進(jìn)行設(shè)計(jì)培訓(xùn)Designing with SystemVerilog
   Who Should Attend?
   FPGA designers and logic designers
2. Course Outline
   ? 1
   Introduction to SystemVerilog
   Data Types
   Lab 1:?SystemVerilog Data Types
   Structures, Unions, and Arrays
   Additional Operators in System Verilog
   Procedural Statements and Flow Control
   Lab 2:?always_ff and always_comb Procedural Blocks
   ? 2
   Functions, Tasks, and Packages
   Interfaces
   Lab 3:?Interfaces and Design Download
   Packages
   Targeting Xilinx FPGAs
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