 PrimeRail培訓 |
| 培養對象 |
1.理工科背景，有志于數字集成電路設計工作的學生和轉行人員；
2.需要充電，提升技術水平和熟悉設計流程的在職人員；
3.集成電路設計企業的員工內訓。
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| 入學要求 |
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學員學習本課程應具備下列基礎知識：
◆電路系統的基本概念。 |
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班級規模及環境--熱線:4008699035 手機:15921673576( 微信同號) |
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每期人數限3到5人。 |
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上課時間和地點 |
上課地點：【上海】：同濟大學(滬西)/新城金郡商務樓(11號線白銀路站) 【深圳分部】：電影大廈(地鐵一號線大劇院站)/深圳大學成教院 【北京分部】：北京中山學院/福鑫大樓 【南京分部】：金港大廈(和燕路) 【武漢分部】：佳源大廈（高新二路） 【成都分部】：領館區1號（中和大道） 【沈陽分部】：沈陽理工大學/六宅臻品 【鄭州分部】：鄭州大學/錦華大廈 【石家莊分部】：河北科技大學/瑞景大廈 【廣州分部】：廣糧大廈 【西安分部】：協同大廈
最近開課時間(周末班/連續班/晚班）： PrimeRail培訓開班時間：2020年3月16日 |
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實驗設備 |
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專注高端培訓15年，端海提供的證書得到本行業的廣泛認可，學員的能力
得到大家的認同，受到用人單位的廣泛贊譽。
★實驗設備請點擊這兒查看★ |
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最新優惠 |
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◆請咨詢客服。 |
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質量保障 |
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1、培訓過程中，如有部分內容理解不透或消化不好，可免費在以后培訓班中重聽；
2、培訓結束后,授課老師留給學員聯系方式,保障培訓效果,免費提供課后技術支持。
3、培訓合格學員可享受免費推薦就業機會。 |
PrimeRail培訓 |
第一階段 |
ObjectivesAt the end of this workshop the student should be able to:
- Set up and perform Power/Ground (PG) reliability analysis for checking Static and Dynamic Voltage Drop and Electromigration (EM) potential violations
- Explanation of and/or set up the phases of Dynamic analysis of PrimeRail that involve the following:
- Library Characterization
- Data preparation
- Power Analysis
- PG Parasitic (RC) Extraction
- Dynamic (Transient) Rail Analysis
- Violation Viewing, Reporting and Correction
- What-if Analysis ? Package parasitics and Decap insertion
- Voltage Drop Derated Timing Analysis
- Accurate Hard Macro Modeling
- Power Management( power switch) Cell handling
- Set up PG analysis for hierarchical and top-level
- Use the PrimeRail graphical user interface (GUI) for the PG rail analysis, including what-if analysis
Audience Profile
Design, verification or CAD engineers who perform power/ground interconnect reliability analysis at the "Block" or "Full-Chip" levels. This covers a wide spectrum of designs of digital, memory, and analog/mixed signal.Prerequisites
Experience in the following areas is recommended to gain the most value from the workshop content:
- Physical layout
- Physical extraction
- Power simulation
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Static Analysis
- Introduction to Rail Analysis - requirements, capabilities and database preparation
- Power and Timing Model creation
- Power supply, net switching and Transition Time inputs
- Power and Rail Analysis
- Mapping, reporting, querying and what-if Analysis
- Integrated Flows - Hardmacro modeling, Power gating and Voltage derated timing analysis
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第二階段 |
Dynamic ( Transient) Analysis
- Introduction, database requirements and flows
- Library Characterization and LSF
- Cell-Level Dynamic Analysis-PP Run
- Cell-Level Dynamic Analysis-Transient Analysis
- What-if Analysis ? Package Parasitics and Decap Insertion
- Mapping, waveform viewing, reporting and querying
- Tx-Level Dynamic Analysis-Data Preparation
- Tx-Level Dynamic Analysis
- Tx-Level Signal EM Analysis
- Macro Modeling - Memory, Analog, custom or Hardmacro blocks
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